| Title: | Serial IIR filter structure generator for ASICs |
| Authors: | Pristach, Marián Fujčík, Lukáš |
| Citation: | Electroscope. 2012, č. 6, EDS 2012. |
| Issue Date: | 2012 |
| Publisher: | Západočeská univerzita v Plzni, Fakulta elektrotechnická |
| Document type: | konferenční příspěvek conferenceObject |
| URI: | http://hdl.handle.net/11025/1045 http://147.228.94.30/images/PDF/Rocnik2012/Cislo6_2012/r6c6c5.pdf |
| ISSN: | 1802-4564 |
| Keywords: | digitální filtry s nekonečnou impulzní odezvou;generátory;integrované obvody |
| Keywords in different language: | infinite impulse response digital filters;generators;integrated circuits |
| Abstract in different language: | The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file. |
| Rights: | © 2012 Electroscope. All rights reserved. |
| Appears in Collections: | Číslo 6 - EDS 2012 (2012) Číslo 6 - EDS 2012 (2012) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| r6c6c5.pdf | 277,88 kB | Adobe PDF | View/Open |
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