Název:	FPGA-based real-time HIL simulator of permanent magnet synchronous motor drive
Autoři:	Janouš, Štěpán Talla, Jakub Košan, Tomáš Peroutka, Zdeněk
Citace zdrojového dokumentu:	JANOUŠ, Š. TALLA, J. KOŠAN, T. PEROUTKA, Z. FPGA-based real-time HIL simulator of permanent magnet synchronous motor drive. In 2021 IEEE 19th International Power Electronics and Motion Control Conference (PEMC) : /proceedings/. Piscaway: IEEE, 2021. s. 552-558. ISBN: 978-1-72815-660-6
Datum vydání:	2021
Nakladatel:	IEEE
Typ dokumentu:	konferenční příspěvek ConferenceObject
URI:	2-s2.0-85107501810 http://hdl.handle.net/11025/46660
ISBN:	978-1-72815-660-6
Klíčová slova v dalším jazyce:	semiconductor device modeling;computational modeling;predictive models;permanent magnet motors;synchronous motors;real-time systems;hardware
Abstrakt v dalším jazyce:	In a real-time control systems, reliability plays a key role. This topic is closely related to a control algorithm design as well as its effective implementation. The In the Loop testings such as Model In the Loop (MIL), Software In the Loop (SIL), Processor In the Loop (PIL) and Hardware In the Loop (HIL) are the popular methods for verification and validation of embedded systems in different stage of development. Especially, HIL is the popular way of embedded system verification in a real-time conditions. For HIL realtime models of electric drives with incorporation of inverter switching, dead-time effects etc. the field programmable gate arrays (FPGAs) are the most popular target hardware platform. This paper is focused on development of the real-time HIL simulator of permanent magnet synchronous motor (PMSM) drive, containing detailed model of PMSM motor together with the model of the power converter. It allows us to address usually un-modeled phenomenons such as dead-times, voltage drops on the semiconductor components as well as nonlinear magnetic characteristics. The algorithm is implemented in low cost FPGA and in order to minimize the computational time, a fixed point calculation together with high level of pipelining is used. The developed HIL simulator is tested and the results are validated by comparison with the real laboratory drive with the identical parameters.
Práva:	Plný text je přístupný v rámci univerzity přihlášeným uživatelům. © IEEE
Vyskytuje se v kolekcích:	Konferenční příspěvky / Conference papers (RICE) Konferenční příspěvky / Conference Papers (KEV) OBD

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