Full metadata record
| DC pole | Hodnota | Jazyk |
|---|---|---|
| dc.contributor.author | Urban, Ondřej | |
| dc.contributor.author | Georgiev, Vjačeslav | |
| dc.contributor.author | Zich, Jan | |
| dc.date.accessioned | 2022-03-07T11:00:24Z | - |
| dc.date.available | 2022-03-07T11:00:24Z | - |
| dc.date.issued | 2021 | |
| dc.identifier.citation | URBAN, O. GEORGIEV, V. ZICH, J. Fast FPGA-based serial receiver design. In 2021 29th Telecommunications Forum (TELFOR) : Proceedings. Piscataway: IEEE, 2021. s. 1-4. ISBN: 978-1-66542-584-1 | cs |
| dc.identifier.isbn | 978-1-66542-584-1 | |
| dc.identifier.uri | 2-s2.0-85124608390 | |
| dc.identifier.uri | http://hdl.handle.net/11025/47096 | |
| dc.format | 4 s. | cs |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | en |
| dc.publisher | IEEE | en |
| dc.relation.ispartofseries | 2021 29th Telecommunications Forum (TELFOR) : Proceedings | en |
| dc.rights | Plný text je přístupný v rámci univerzity přihlášeným uživatelům. | cs |
| dc.rights | © IEEE | en |
| dc.title | Fast FPGA-based serial receiver design | en |
| dc.type | konferenční příspěvek | cs |
| dc.type | ConferenceObject | en |
| dc.rights.access | restrictedAccess | en |
| dc.type.version | publishedVersion | en |
| dc.description.abstract-translated | This paper describes a fast serial digital signal receiver for applications in nuclear instrumentation. The proposed design uses a Microsemi Polarfire FPGA embedded Ethernet transceiver for data oversampling (with frequency up to 12.7 GHz) and deserialization. The subsequent FPGA implemented digital signal processing chain then analyses the oversampled data array (at least 4 samples per data bit are required by the processing logic). This processing chain begins with a frame buffer, which ensures that the entire sampled data frame can be captured and a 5-bit majority parallel filter. Following start sequence detection logic uses a comparator array for valid data triggering and data offset evaluation. These information are then used by the sampling point selection logic for data restoration. Thanks to the single clock cycle operation of each of these logic blocks, the processing chain provides a constant propagation delay and no dead time is required between individual data frames. The device prototype based on this design is described and measurement results for a data bit rate of 400 MHz and a sampling rate of 3.2 GHz are presented. | en |
| dc.subject.translated | serial communication | en |
| dc.subject.translated | FPGA | en |
| dc.subject.translated | transceiver | en |
| dc.subject.translated | ethernet | en |
| dc.subject.translated | data reconstruction | en |
| dc.subject.translated | NIM | en |
| dc.identifier.doi | 10.1109/TELFOR52709.2021.9653394 | |
| dc.type.status | Peer-reviewed | en |
| dc.identifier.obd | 43934912 | |
| dc.project.ID | EF16_019/0000766/Inženýrské aplikace fyziky mikrosvěta | cs |
| dc.project.ID | LM2015058/Výzkumná infrastruktura pro experimenty CERN | cs |
| dc.project.ID | LTT17018/Získávání nových poznatků o mikrosvětě v infrastruktuře CERN | cs |
| Vyskytuje se v kolekcích: | Konferenční příspěvky / Conference papers (RICE) Konferenční příspěvky / Conference Papers (KEI) OBD | |
Soubory připojené k záznamu:
| Soubor | Velikost | Formát | |
|---|---|---|---|
| Urban_Fast_FPGA-based.pdf | 751,69 kB | Adobe PDF | Zobrazit/otevřít |
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