Title: | Hardware-accelerated collision detection using bounded-error fixed-point arithmetic |
Authors: | Raabe, Andreas Hochgürtel, Stefan Anlauf, Joachim K. Zachmann, Gabriel |
Citation: | Journal of WSCG. 2006, vol. 14, no. 1-3, p. 17-24. |
Issue Date: | 2006 |
Publisher: | Václav Skala - UNION Agency |
Document type: | článek article |
URI: | http://wscg.zcu.cz/wscg2007/Papers_2007/journal/!WSCG2007_Journal_Final.zip http://hdl.handle.net/11025/1356 |
ISBN: | 80-86943-09-7 |
ISSN: | 1213-6972 (hardcopy) 1213-6964 (online) 1213-6980 (CD-ROM) |
Keywords: | hardwarově akcelerovaná detekce kolizí;grafické objekty;aritmetika pevného bodu |
Keywords in different language: | hardware-accelerated collision detection;graphic objects;fixed-point arithmetic |
Abstract: | A novel approach for highly space-efficient hardware-accelerated collision detection is presented. This paper focuses on the architecture to traverse bounding volume hierarchies in hardware. It is based on a novel algorithm for testing discretely oriented polytopes (DOPs) for overlap, utilizing only fixed-point (i.e., integer) arithmetic. We derive a bound on the deviation from the mathematically correct result and give formal proof that no false negatives are produced. Simulation results show that real-time collision detection of complex objects at rates required by force-feedback and physicallybased simulations can be obtained. In addition, synthesis results prove the architecture to be highly space efficient. We compare our FPGA-optimized design with a fully parallelized ASIC-targeted architecture and a software implementation. |
Rights: | © Václav Skala - UNION Agency |
Appears in Collections: | Number 1-3 (2006) |
Please use this identifier to cite or link to this item:
http://hdl.handle.net/11025/1356
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