Název:	NEON: Near-accurate efficient FIR Filter for ultra low-power applications
Autoři:	Inapurapu, Srimai Ravindra, Jvr
Citace zdrojového dokumentu:	2016 International Conference on Applied Electronics: Pilsen, 6th – 7th September 2016, Czech Republic, p.97-101.
Datum vydání:	2016
Nakladatel:	Západočeská univerzita v Plzni
Typ dokumentu:	konferenční příspěvek conferenceObject
URI:	http://hdl.handle.net/11025/35198
ISBN:	978–80–261–0601–2 (Print) 978–80–261–0602–9 (Online)
ISSN:	1803–7232 (Print) 1805–9597 (Online)
Klíčová slova:	sčítání;filtry konečných impulsních odezev;logická brána;neon;zpoždění;ztráta výkonu;multimediální komunikace
Klíčová slova v dalším jazyce:	adders;finite impulse response filters;logic gate;Neon;delays;power dissipation;multimedia communication
Abstrakt v dalším jazyce:	Low-power dissipation is an imperative requirement in the design of an efficient Digital Signal Processing system which is employed in many multimedia applications such as image and video processing. Finite Impulse Response (FIR) filter is indispensable in the design of several such Digital Signal Processing (DSP) applications. The output of these applications, either an image or a video can be nearly accurate for human perception. This toleration in the loss of quality of the output can be exploited to design an energy-efficient system by using approximate computation. Moreover, the efficacy of a system can be improved multi-fold by using reversible logic which benefits in the design of ultra-low-power systems. In this paper, we propose an approximate adder using a reversible Toffoli gate and employ it in designing NEON (Near-accurate and Efficient FIR filter for ultra low-power applicatiONs). Simulation results carried out using Cadence© design tools in 45nm technology node show that the FIR Filter designed using the proposed adder gives significantly better results compared to the designs using the adders in literature. Experiment results using ISCAS benchmarks and comparison with previous methods demonstrate the effectiveness of the proposed method. In addition to producing fewer garbage outputs, the FIR filter designed using the proposed adder yields power reduction of 74%, delay reduction of 64% and Power-Delay Product reduction of 90.1%.
Práva:	© Západočeská univerzita v Plzni
Vyskytuje se v kolekcích:	Applied Electronics 2016 Applied Electronics 2016

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