| Title: | Performance analysis of monolithically integrated depletion-/enhancement-mode InAlN/GaN heterostructure HEMT transistors |
| Authors: | Nagy, Lukáš Chvála, Aleš Stopjaková, Viera Blaho, Michal Kuzmík, Ján Gregušová, Dagmar Šatka, Alexander |
| Citation: | 2017 International Conference on Applied Electronics: Pilsen, 5th – 6th September 2017, Czech Republic, p.129-132. |
| Issue Date: | 2017 |
| Publisher: | Západočeská univerzita v Plzni |
| Document type: | konferenční příspěvek conferenceObject |
| URI: | http://hdl.handle.net/11025/35425 |
| ISBN: | 978–80–261–0641–8 (Print) 978–80–261–0642–5 (Online) |
| ISSN: | 1803–7232 (Print) 1805–9597 (Online) |
| Keywords: | heterostruktura InAlN / GaN;monolitická integrace;HEMT tranzistor;digitální měnič |
| Keywords in different language: | digital inverter;InAlN/GaN Heterostructure;monolithic integration;HEMT transistor |
| Abstract in different language: | The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is presented as well. The proposed mask set was designed taking into account the design-for-manufacturing approach. Furthermore, we evaluated measured properties and performance of the fabricated transistors and circuits and recalibrate the transistor models according to the latest measurements. |
| Rights: | © Západočeská univerzita v Plzni |
| Appears in Collections: | Applied Electronics 2017 Applied Electronics 2017 |
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